1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to improved methods for processing a semiconductor topography having a substantially planar upper surface.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabrication of an integrated circuit involves numerous processing steps. After implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the implant regions from overlying conducting regions. Interconnect routing is then placed over the interlevel dielectric and connected to the implant regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
Forming substantially planar upper surfaces of a semiconductor topography during intermediate process steps may facilitate fabrication of layers and structures that meet design specifications. For example, a dielectric layer may be formed across a previously patterned layer of a semiconductor topography using a process such as chemical vapor deposition (xe2x80x9cCVDxe2x80x9d). Elevational disparities of the deposited dielectric layer may be reduced by planarizing the deposited dielectric layer using a process such as chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d). A contact opening may be formed within the planarized dielectric layer and subsequently filled with a layer of conductive material. In this manner, the layer of conductive material may be formed within the contact opening and on an upper surface of the planarized dielectric layer. As such, the layer of conductive material may also be planarized such that an upper surface of the contact structure may be substantially planar with an upper surface of the dielectric layer.
Additional layers and structures may be formed upon the contact structures and the dielectric layer. The additional layers and structures may include, for example, additional dielectric layers, additional contact structures, local interconnect wires, and/or metallization layers. In this manner, the planarized upper surface of the contact structures and the dielectric layer may facilitate the formation of such additional layers and structures having uniform vertical and lateral dimensions. For example, the planarization of the semiconductor topography may facilitate the formation of local interconnect structures having a substantially uniform thickness by providing a planar surface upon which a dielectric material may be deposited to insulate adjacent local interconnect structures. Moreover, the planarization of the semiconductor topography may aid in forming local interconnect structures having uniform lateral dimension by providing a planar surface upon which a patterned masking layer may be formed. In this manner, a masking layer may be accurately patterned by a lithography technique such that the pattern may be accurately transferred to a dielectric layer to form local interconnect structures. Accordingly, layers and structures of a semiconductor device may be formed having dimensions which are approximately equal to design specifications for the semiconductor device.
Forming a substantially planar upper surface of such layers and structures may play an important role in the functionality of a semiconductor device. For example, problems with step coverage may arise when a dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a semiconductor topography may increase with reductions in feature size. If a topography is nonplanar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational xe2x80x9chillxe2x80x9d or xe2x80x9cvalleyxe2x80x9d area. The presence of such elevational disparities therefore makes it difficult to print high-resolution features.
As mentioned above, CMP is a technique commonly employed to planarize or remove the elevational fluctuations in the surface of a semiconductor topography. A conventional CMP process may involve placing a semiconductor wafer facedown on a polishing pad, which lies on or is attached to a rotatable table or platen. A typical polishing pad medium may include polyurethane or polyurethane-impregnated polyester felts. During the CMP process, the polishing pad and the semiconductor wafer may be rotated relative to each other as the wafer is forced against the pad. An abrasive, fluid-based chemical suspension, often referred to as a xe2x80x9cslurry,xe2x80x9d may be deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The rotational movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. Alternatively, a liquid substantially free of particulate matter may be deposited onto the polishing pad during polishing. In addition, the pad itself may physically remove some material from the surface of the semiconductor topography. Therefore, the process may employ a combination of chemical stripping and mechanical polishing to form a planarized surface.
Unfortunately, a CMP process may not form a substantially planar surface across an entire semiconductor topography. For example, if the polishing rate of CMP varies across a topography, a planarized semiconductor topography may have substantial elevational disparities. Such disparities may be particularly prevalent at an edge of the topography. For example, a thickness of a semiconductor topography may be greater at the edge of the topography than at an inner portion of the topography. The greater thickness of the semiconductor topography at its edge may be due to a slow polish rate at the edge of the topography as compared to polish rates at other regions of the topography. Several factors may influence the polish rates of a CMP process. For example, the polish rates may depend on the pressure used to force the semiconductor topography against a polishing pad during CMP. The pressure may be greater near the inner portion of the wafer than at the edge of the wafer. In fact, the edge of the semiconductor topography may not contact the pad due to pad distortions that may occur from the pressure used to force the topography against the pad. In this manner, the outer portions of the semiconductor topography may not be polished at the same rate as inner portions of the semiconductor topography. Additional factors which may affect polish rates of the CMP process may include the polishing tool, the pad materials, the slurry, the surface materials being polished, and the rotational and lateral movement of the polishing pad relative to the semiconductor topography.
Elevational disparities which may be present on a semiconductor topography subsequent to chemical mechanical polishing may inhibit the formation of semiconductor devices on a portion of the semiconductor topography. For example, a thickness of the semiconductor topography may be greater at an outer edge of the semiconductor topography than at an inner portion of the semiconductor topography. As such, the thickness of the semiconductor topography at the outer edge may be outside of design specifications for a semiconductor device. Consequently, semiconductor devices formed at the outer edge of such a semiconductor topography may have dimensions which deviate significantly from design specifications. In this manner, acceptable devices may not be formed on an area of the semiconductor topography having such elevational disparities, thereby reducing the number of devices which may be formed on the semiconductor topography. As such, the presence of such elevational disparities on a semiconductor topography may reduce manufacturing yield and may increase production costs per semiconductor device.
Accordingly, it would be advantageous to develop a method for forming a semiconductor topography having a substantially planar upper surface across substantially the entire semiconductor topography including its outer edge.
The problems outlined above may be in large part addressed by a method for processing a semiconductor topography such that its upper surface is substantially planar. In particular, a method is provided in which a substantially planar upper surface in a region adjacent to an outer edge of a semiconductor topography may be formed. According to an embodiment, the method may include preferentially removing a portion of an upper layer of the topography in a region adjacent to an outer edge of the semiconductor topography. The removed portion may extend greater than approximately 3 mm inward from the outer edge of the semiconductor topography. In one embodiment, the removed portion may extend approximately 6 mm inward from the outer edge of the semiconductor topography. Removing the upper layer may include etching a portion of the upper layer. For example, the removed portion may have an average thickness of approximately 5% to approximately 30% of the average thickness of the upper layer. The method may also include polishing the semiconductor topography such that the upper surface of the semiconductor topography is substantially planar. In this manner, the thickness of the polished upper layer of the semiconductor topography may be approximately the same across the entirety of the semiconductor topography. Therefore, although a rate of polishing adjacent to an outer edge of the semiconductor topography may be slower than a rate of polishing adjacent to a center of the semiconductor topography, a thickness variation of the polished upper layer across the entirety of the semiconductor topography may be less than approximately 500 angstroms. In one embodiment, the thickness variation of the polished upper layer across the entirety of the semiconductor topography may be less than approximately 125 angstroms.
In an embodiment, the semiconductor topography may include a semiconductor substrate such as a monocrystalline silicon substrate. Such a substrate may preferably be in the form of a semiconductor wafer. The semiconductor topography may further include a plurality of structures and/or layers formed upon a semiconductor substrate. The structures and layers may include, but are not limited to, gate structures, local interconnect, vias, metallization layers, and dielectric layers formed upon the silicon substrate. Furthermore, the semiconductor topography may include diffusion regions or shallow trench isolation regions formed within a semiconductor substrate or within a layer formed upon a substrate. For example, a shallow trench isolation region may include a trench formed in a silicon substrate. A silicon nitride layer may be formed upon the silicon substrate and adjacent to the trenches. A pad oxide layer may also be formed upon the silicon substrate to promote adhesion of the silicon nitride layer to the silicon substrate. In addition, silicon dioxide, or another appropriate dielectric material, may be formed within the trench and upon the silicon nitride layer adjacent to the trenches.
The upper layer adjacent to the outer edge of the semiconductor topography, as described above, may include an intermetal dielectric layer or a polymetal dielectric layer. For example, the upper layer may include a dielectric material, such as silicon dioxide (SiO2), tetraorthosilicate glass (TEOS), silicon nitride (SixNy), silicon oxynitride (SiOxNy(Hz)), or silicon dioxide/silicon nitride/silicon dioxide (ONO). Additionally, the dielectrics may be undoped or may be doped, for example, with boron, phosphorus, boron and phosphorus, or fluorine, to form a doped dielectric layer such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), and fluorinated silicate glass (FSG). The dielectrics may be deposited by physical deposition such as sputtering or by a variety of chemical deposition methods and chemistries such as chemical vapor deposition. Alternatively, the upper layer may include a conductive material such as polysilicon, a metal, such as aluminum, copper, or titanium, or a metal alloy, which may also be deposited by similar physical deposition and chemical deposition techniques.
In an additional embodiment, the upper layer may be formed upon a lower semiconductor layer having a plurality of nonplanar structures formed upon and spaced across the semiconductor topography. For example, the upper layer may include a dielectric layer conformally deposited over a plurality of trenches formed within and spaced across a semiconductor topography. Furthermore, the upper layer may be formed upon another substantially planar layer formed upon the semiconductor topography. In this manner, the upper layer may include a metallization layer overlying an entire semiconductor topography. In one embodiment, the upper layer may be formed upon and in contact with a polish stop layer. For example, the polish stop layer may be formed upon an upper surface of the semiconductor topography and adjacent to features formed in the semiconductor topography such as trenches. The polish stop layer may include, for example, silicon nitride. Appropriate materials for a polish stop layer, however, may also include any material having a substantially different polish response than the upper layer. In this manner, polishing may include exposing an upper surface of the polish stop layer. As such, subsequent to polishing, an upper surface of the upper layer within a trench formed in the semiconductor topography may be substantially coplanar with an upper surface of the polish stop layer. Alternatively, subsequent to polishing, an upper surface of the upper layer may be below an upper surface of a polish stop layer formed adjacent to the trench.
The method may also include forming a resist upon the upper layer and removing the resist in a region adjacent to the outer edge of the semiconductor topography to expose the upper layer prior to etching the portion of the upper layer in a region adjacent to the outer edge of the semiconductor topography. As such, the resist may be removed adjacent to the outer edge of the semiconductor topography such that the upper layer may be exposed and subsequently etched. In this manner, the resist may remain on the upper layer of the semiconductor topography to substantially mask the upper layer adjacent to the region to be preferentially removed. Thus, only the exposed portion of the upper layer adjacent to the outer edge of the semiconductor topography may be etched. A number of techniques may be used to remove the resist adjacent to the outer edge of the semiconductor topography. For example, an edge bead removal chemical may be applied to the resist adjacent to an outer edge of the semiconductor topography to remove the resist. Alternatively, the resist may be removed by exposing the resist adjacent to the outer edge of the semiconductor topography and applying a developer to the exposed portions. As such, removing the resist adjacent to an outer edge of the semiconductor topography may involve a chemical or an optical method. The resist may include a photoresist, such as a deep ultraviolet resist, an I-line resist, a G-line resist, or another resist, such as an e-beam resist or an x-ray resist.
The process of preferentially removing the upper layer may include removing a portion of the upper layer such that the upper layer in a region adjacent to the outer edge of the semiconductor topography may be recessed as compared to the thickness of other regions of the upper layer. For example, if the initial thickness of the upper layer is approximately 6,000 angstroms to approximately 10,000 angstroms, the method may include reducing a thickness of the upper layer by approximately 1,200 angstroms. In addition, a region of the upper layer extending greater than approximately 3 mm inward from the outer edge of the semiconductor topography may be removed. In one embodiment, the region of the upper layer extending laterally from the outer edge of the semiconductor topography may be approximately 6 mm. The initial thickness of the upper layer and a thickness of the removed portion of the upper layer may vary, however, depending on the design specifications of the device. For example, a thickness of the portion of the upper layer that is removed may be optimized such that a substantially planar upper surface of the semiconductor topography may be obtained subsequent to a polishing process. The etch process may include a wet etch process using HF and/or NH4F. Alternatively, a plasma etch process may be employed which may involve using CF4, CHF3, C2F6, SF6, NF3, O2, Ar, and N2 as etchant gases. Subsequent to removing the upper layer adjacent to the outer edge of the semiconductor topography, the resist may be removed by a wet etch or stripping process.
As such, a semiconductor topography may include an upper layer formed conformally upon a non-planar lower semiconductor layer. An average thickness of the upper layer in a region adjacent to an outer edge of the semiconductor topography may be less than an average thickness of the upper layer in a region including a center of the topography. For example, the average thickness of the upper layer within the region adjacent to the outer edge of the semiconductor topography may be approximately 5% to approximately 30% less than the average thickness of the upper layer in a region including a center of the topography. The region may extend greater than approximately 3 mm inward from the outer edge of the semiconductor topography. In one embodiment, the region extending laterally from the outer edge of the semiconductor topography may be approximately 6 mm.
A thickness of the removed portion of the upper layer may depend on the initial thickness of the upper layer and a rate of a subsequent polishing step. Polishing may include a CMP process. Unfortunately, the polishing rate across a semiconductor topography may vary depending on a number of variables involved in a CMP process. For example, the polishing rate adjacent to the outer edge of the semiconductor topography may be slower than the polishing rate adjacent to the center of the semiconductor topography. A polishing rate discrepancy across a semiconductor topography may be determined by comparing a thickness of the upper layer across the semiconductor topography subsequent to polishing. Consequently, a thickness of the removed portion of the upper layer may be determined based on the polishing rate across a semiconductor topography such that a semiconductor topography having a substantially planar surface may be formed.
A substantially planar surface may have a thickness variation across the entirety of the polished semiconductor topography which does not vary substantially. For instance, the method as described herein may produce a substantially planar surface, which has a thickness variation across the entirety of the semiconductor topography, including a region adjacent to an outer edge of the semiconductor topography, of less than approximately 500 angstroms and more preferably less than approximately 120 angstroms. There may be several advantages to forming a substantially planar upper surface upon a semiconductor topography. For example, a semiconductor device may be formed approximately 4 mm from the outer edge of a semiconductor substrate. The formation of semiconductor devices within such a relatively close vicinity of the outer edge of the substrate may allow for an increase in the number of devices that may be formed upon a substrate. Such an increase in semiconductor device formation upon a substrate may increase manufacturing yield and may reduce production costs per semiconductor device.
A semiconductor topography formed by the method is also contemplated herein. The semiconductor topography may include a polished layer formed over a semiconductor wafer. The polished layer may include a plurality of structures laterally arranged across the semiconductor wafer. The structures may include, for example, gate structures, contact structures, local interconnect structures, conductive plugs, shallow trench isolation structures, dielectric layers, and conductive layers. A thickness of a structure arranged within a region adjacent to an outer edge of the semiconductor topography may differ by less than approximately 500 angstroms from a thickness of a corresponding structure arranged in a region including a center of the topography. In one embodiment, the thickness variation between a structure arranged within a region adjacent to an outer edge of the semiconductor topography and a corresponding structure arranged in a region including a center of the topography may vary by approximately 125 angstroms. The region adjacent to the outer edge may extend greater than approximately 3 mm laterally from the outer edge of the semiconductor topography. In one embodiment, the region extending laterally from the outer edge of the semiconductor topography may be approximately 6 mm. The structure arranged in a region adjacent to an outer edge may include at least a portion of a semiconductor device. Such a semiconductor topography may include, therefore, a semiconductor device arranged in a region approximately 4 mm extending laterally from the outer edge of the semiconductor topography.